1. Field of the Invention
This invention relates to a liquid crystal display device, and more particularly to a horizontal electric field switching liquid crystal display device and a fabricating method thereof. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for a horizontal electric field switching liquid crystal display (LCD) device formed using a reduced number of masking processes having increased capacitance.
2. Description of the Related Art
Generally, a liquid crystal display device controls light transmittance of a liquid crystal molecules having a dielectric anisotropy using an electric field to thereby display a picture. The liquid crystal molecules are positioned between upper and lower substrates. Such LCD devices are classified as either a vertical electric field switching type or a horizontal electric field switching type depending upon the direction of the electric field driving the liquid crystal molecules.
The LCD device of the vertical electric field switching type can drive the liquid crystal molecules in a twisted nematic (TN) mode with a vertical electric field formed between a pixel electrode and a common electrode arranged in opposition to each other on the upper and lower substrates. Such a TN mode LCD device has the advantage of a large aperture ratio. However, the TN mode LCD device has the drawback of a narrow viewing angle that is about 90°.
The LCD device of a horizontal electric field switching type can drive a the liquid crystal molecules in an in-plane switching (IPS) mode or with a horizontal electric field between the pixel electrode and the common electrode arranged in parallel to each other on the lower substrate. Such an IPS mode LCD device has the advantage of a wide viewing angle, which is about 160°. Hereinafter, a related art IPS mode LCD device will be described in detail.
A related art IPS mode LCD device includes a thin film transistor array substrate (lower substrate) and a color filter array substrates (upper substrate) that are opposed to each other, a spacer for constantly keeping a cell gap between the two substrates, and a layer of liquid crystal molecules within the cell gap. The thin film transistor array substrate includes a plurality of signal wirings and thin film transistors, and an upper alignment film coated thereon to align the liquid crystal molecules. The color filter array substrate includes a color filter for implementing color, a black matrix for preventing light leakage and an upper alignment film coated thereon to align the liquid crystal molecules.
Fabrication of the thin film transistor array substrate includes semiconductor processes that require a plurality of mask processes. Each of the mask processes are complicated fabricating processes that add to the manufacturing cost of the liquid crystal display panel. One mask process includes many process steps, such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping and an inspection processes. To reduce manufacturing cost, a thin film transistor array substrate has been developed, which can be made with a reduced number of mask processes. For example, reducing a standard five-round mask process for forming a thin film transistor substrate to a four-round mask process for forming a thin film transistor array substrate has been suggested recently.
FIG. 1 is a plan view showing a portion of a thin film transistor array substrate of an IPS mode liquid crystal display device formed by a related art four-round mask process, and FIG. 2 is a cross-sectional view of the thin film transistor array substrate along the lines I-I′ and II-II′ in FIG. 1. As shown in FIG. 1 and FIG. 2, the thin film transistor array substrate includes a gate line 2 and a data line 4 provided on a lower substrate 45 in such a manner to cross each other with a gate insulating film 46 therebetween. A thin film transistor 6 is formed at each crossing of a gate line 2 and a data line 4. A pixel electrode 14 and a common electrode 18 are formed in such a manner on the thin film transistor array substrate to provide a horizontal electric field in a pixel area defined by the gate line 2 and a data line 4. A common line 16 is connected to the common electrode 18. A storage capacitor 20 is formed by a portion of the pixel electrode 14 that overlaps a common electrode line 16. A gate pad 24 is connected to the gate line 2. A data pad 33 is connected to the data line 4. A common pad 36 is connected to the common line 16.
The data line 4 supplies a data signal to the pixel electrode 14 through the thin film transistor 6 while the gate line 2 supplies a gate signal. More specifically, the thin film transistor 6 allows a pixel signal applied to the data line 4 to be charged onto the pixel electrode 14 in response to a scanning signal applied to the gate line 2. The common line 16 supplies a reference voltage for driving the liquid crystal and is formed in parallel to the gate line 2.
The thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4 and a drain electrode 12 connected to the pixel electrode 14. The thin film transistor 6 also includes an active layer 48 overlapping the gate electrode 8 with a gate insulating film 46 therebetween. The active layer 48 has a channel between the source electrode 10 and the drain electrode 12. Other active layers 48 are formed in such a manner as to respectively overlap the data line 4, a lower data pad electrode 32 and an upper storage electrode 22. Further, the data line 4, the source electrode 10, the drain electrode 12, the lower data pad electrode 32 and an ohmic contact layer 50 for making an ohmic contact with the upper storage electrode 22 are provided on the active layers 48.
The pixel electrode 14 is formed in the pixel area and connected, via a first contact hole 13 passing through a protective film 52, to the drain electrode 12 of the thin film transistor 6. More particularly, the pixel electrode 14 includes a first horizontal portion 14A connected to the drain electrode 12 and formed in parallel to the adjacent gate line 2, a second horizontal portion 14B formed in such a manner as to overlap the common line 16 and finger portions 14C formed in parallel between the first and second horizontal portions 14A and 14B. The common electrode 18 is connected to the common line 16 and is formed in the pixel area. More particularly, the common electrode 18 has fingers formed in parallel to the finger portions 14C of the pixel electrode 14 in the pixel area.
A horizontal electric field can be formed between the pixel electrode 14, supplied with a pixel signal via the thin film transistor 6, and the common electrode 18, supplied with a reference voltage via the common line 16. More particularly, a horizontal electric field is formed between the finger portions 14C of the pixel electrode 14 and the fingers of the common electrode 18. Liquid crystal molecules are re-arranged or rotated in the horizontal direction between the thin film transistor array substrate and the color filter array substrate by such a horizontal electric field due to a dielectric anisotropy of the liquid crystal molecules. Transmittance of a light transmitting through the pixel area is differentiated depending upon a rotation extent of the liquid crystal molecules, thereby implementing a range of gray levels.
The storage capacitor 20 includes an upper storage electrode 22 overlapping the common line 16 with the gate insulating film 46, the active layer 48 and the ohmic contact layer 50 therebetween. The pixel electrode 14 is connected, via a second contact hole 21 provided on the protective film 52, to the upper storage electrode 22. Such a storage capacitor 20 allows a pixel signal charged onto the pixel electrode 14 to be stably maintained until the next pixel signal is charged.
The gate line 2 is connected, via the gate pad 24, to a gate driver (not shown). The gate pad 24 includes a lower gate pad electrode 26 extending from the gate line 2 and an upper gate pad electrode 28 connected, via a third contact hole 27 passing through the gate insulating film 46 and a protective film 52, to the lower gate pad electrode 26. The data line 4 is connected via the data pad 30 to a data driver (not shown). The data pad 30 includes a lower data pad electrode 32 extending from the data line 4 and an upper data pad electrode 34 connected, via a fourth contact hole 33 passing through the protective film 52, to the lower data pad electrode 32. The common line 16 is supplied, via a common pad 36, with a reference voltage from a reference voltage source (not shown). The common pad 36 is includes a lower common pad electrode 38 extending from the common line 16 and an upper common pad electrode 40 connected, via a five contact hole 39 passing through the gate insulating film 46 and the protective film 52, to the lower common pad electrode 38.
A method of fabricating a thin film transistor array substrate using a four-round mask process having will be described in detail with reference to FIG. 3A to FIG. 3D. As shown in FIG. 3A, a first conductive pattern group including the gate line 2, the gate electrode 8, the lower gate pad electrode 26, the common line 16, the common electrode 18 and the lower common pad electrode 38 is formed on the lower substrate 45 using a first mask process. More particularly, a first and second metal layer 42 and 44 are sequentially disposed on the lower substrate 45 by a deposition technique, such as sputtering, thereby providing a gate metal layer including two metal films. Next, the gate metal layer is patterned by a photolithography process and an etching process using the first mask, thereby providing the first conductive pattern group including the gate line 2, the gate electrode 8, the lower gate pad electrode 26, the common line 16, the common electrode 18 and the lower common pad electrode 38. Herein, the first metal film 42 is formed from an Al-alloy metal etc., and the second metal film 44 is a metal, such as one of Chrome Cr and molybdenum Mo.
Referring to FIG. 3B, a gate insulating film 46 is coated onto the lower substrate 45 provided with the first conductive pattern group. A semiconductor pattern including the active layer 48 and the ohmic contact layer 50, and a second conductive pattern group including the data line 4, the source electrode 10, the drain electrode 12, the lower data pad electrode 32 and the upper storage electrode 22 are formed on the gate insulating film 46 using a second mask process. More particularly, the gate insulating film 46, an amorphous silicon layer, an amorphous silicon layer doped with n+ impurities and a source/drain metal layer are sequentially formed on the lower substrate 45 provided with the first conductive pattern group by a deposition technique, such as PECVD or sputtering. Herein, the gate insulating film 46 is formed from an inorganic insulating material, such as silicon oxide (SiOx) or silicon nitride (SiNx). The source/drain metal is formed of at least one of molybdenum (Mo), titanium (Ti), tantalum (Ta) and Mo-alloy.
Next, a photo-resist pattern is formed on the source/drain metal layer by a photolithography process using the second mask. In this case, the second mask employs a diffractive exposure mask having a diffractive exposure portion corresponding to the position of the channel of the thin film transistor. The portion of photo-resist pattern for the channel has a lower height than other portions, which is later ashed away and used to etch the source/drain electrodes above the channel region.
Next, the source/drain metal layer is patterned by a wet-etching process using the photo-resist pattern, thereby providing a second conductive pattern group including the data line 4, the source electrode 10, the drain electrode 12 integral with the source electrode 10, and the upper storage electrode 22. And then, the amorphous silicon layer doped with n+ impurities and the amorphous silicon layer are simultaneously patterned by a dry-etching process using the same photo-resist pattern, thereby providing the ohmic contact layer 50 and the active layer 48. Subsequently, the portion of the photo-resist pattern having a relatively low height at the channel is removed by an ashing process. Then, a source/drain metal pattern and the ohmic contact layer 50 of the channel are formed by a dry-etching process. After the dry-etching process, the active layer 48 of the channel is exposed, so that the source electrode 10 and the drain electrode 12 are separated from each other. Next, the photo-resist pattern left on the second conductive pattern group is removed by a stripping process.
Referring to FIG. 3C, the protective film 52 having first to fifth contact holes 13, 21, 27, 33 and 39 is formed on the gate insulating film 46 provided with the second conductive pattern group using a third mask process. More particularly, the protective film 52 is formed over the entire gate insulating film 46, including the second conductive pattern group, by a deposition technique, such as PECVD. Next, the protective film 52 is patterned by a photolithography process and etching process using a third mask, thereby providing the first to fifth contact holes 13, 21, 27, 33 and 39. The first contact hole 13 passes through the protective film 52 to expose the drain electrode 12. The second contact hole 21 passes through the protective film 52 to expose the upper storage electrode 22. The third contact hole 27 passes through the protective film 52 and the gate insulating film 46 to expose the lower gate pad electrode 26. The fourth contact hole 33 passes through the protective film 52 to expose the lower data pad electrode 32. The fifth contact hole 39 passes through the protective film 52 and the gate insulating film 46 to expose the lower common pad electrode 38. The source/drain metal is a metal having a high dry-etching ratio, such as a molybdenum Mo. The first, second and fourth contact holes 12, 21 and 33 respectively pass through the drain electrode 12, the upper storage electrode 22 and the lower data pad electrode 32 to expose side surfaces thereof. The protective film 52 is made of an inorganic insulating material identical to the gate insulating film 46, or an organic insulating material, such as an acrylic organic compound having a small dielectric constant, BCB (benzocyclobutene) or PFCB (perfluorocyclobutane).
Referring to FIG. 3D, a third conductive pattern group, including the pixel electrode 14, the upper gate pad electrode 28, the upper data pad electrode 34 and the upper common pad electrode 40, is formed on the protective film 52 using a fourth mask process. More particularly, a transparent conductive layer is coated on the protective film 52 by a deposition technique, such as sputtering. Next, the transparent conductive layer is patterned by a photolithography process and an etching process using a fourth mask, thereby providing the third conductive pattern group including the pixel electrode 14, the upper gate pad electrode 28, the upper data pad electrode 34 and the upper common pad electrode 40. The pixel electrode 14 is electrically connected, via the first contact hole 13, to the drain electrode 12 and is electrically connected, via the second contact hole 21, to the upper storage electrode 22. The upper gate pad electrode 28 is electrically connected, via the third contact hole 37, to the lower gate pad electrode 26. The upper data pad electrode 34 is electrically connected, via the fourth contact hole 33, to the lower data pad electrode 32. The upper common pad electrode 40 is electrically connected, via the fifth contact hole 39, to the lower common pad electrode 38. The transparent conductive layer can be made of one of Indium Tin Oxide (ITO), Tin Oxide (TO) and Indium Zinc Oxide (IZO).
As described-above, a related art thin film transistor array substrate of an IPS mode liquid crystal display device and a fabricating method thereof uses a four-round mask process to reduce the number of mask processes as compared to a five-round mask process and to reduce the manufacturing cost. But, the four-round mask process has a drawback in that the capacitance capability with respect to the pixel electrode is small. Therefore, a horizontal electric field switching liquid crystal display device having increased capacitance and a fabricating process using four or less mask-rounds is needed to improve performance and/or further reduce the manufacturing cost.